Driving device and operation method thereof

ABSTRACT

A driving device and an operation method thereof are provided. The driving device drives a plurality of light-emitting control lines of an organic light emitting diode (OLED) display panel. The light-emitting control lines are divided into a plurality of groups. The driving device includes a control circuit and a plurality of logic gates. The control circuit generates a global light-emitting control signal and determines a duty cycle of the global light-emitting control signal. Any one of the logic gates determines whether to transmit the global light-emitting control signal to the light-emitting control lines of a corresponding group among the groups. When the global light-emitting control signal is transmitted to a corresponding light-emitting control line among the light-emitting control lines, a pulse of the global light-emitting control signal may light up a plurality of pixels connected to the corresponding light-emitting control line.

BACKGROUND Field of the Invention

The invention relates to a display device and more particularly, to adriving device and an operation method thereof.

Description of Related Art

Generally, in addition to a plurality of data lines and a plurality ofscan lines, an organic light-emitting diode (OLED) display panel alsoincludes a plurality of light-emitting control lines. A driving devicemay scan these scan lines, so as to write a plurality of gray scaleinformation (pixel voltages) into different pixel units (pixel circuits)of the OLED display panel through the data lines. The driving device maydrive the light-emitting control lines of the OLED display panel, so asto light up the pixel units connected to the light-emitting controllines.

Generally, these light-emitting control lines of the OLED display panelare connected to a shift register. A plurality of logical values in alight-emitting control signal of the driving device are input into theshift register in a serial manner. The shift register is like aserial-in and parallel-out (SIPO) circuit. Based on a trigger by a clocksignal, the light-emitting control signal may shift between a pluralityof registers of the shift register, and the registers of the shiftregister may output the light-emitting control signal to thelight-emitting control lines of the OLED display panel. In general, aduration of a period of the clock signal is a line time of the OLEDdisplay panel.

It should be noted that the contents of the section of “Description ofRelated Art” is used for facilitating the understanding of theinvention. A part of the contents (or all of the contents) disclosed inthe section of “Description of Related Art” may not pertain to theconventional technology known to the persons with ordinary skilled inthe art. The contents disclosed in the section of “Description ofRelated Art” do not represent that the contents have been known to thepersons with ordinary skilled in the art prior to the filing of thisinvention application.

SUMMARY

The invention provides a driving device and an operation method thereoffor driving an organic light emitting diode (OLED) display panel.

A driving device of the invention is configured to drive a plurality oflight-emitting control lines of an OLED display panel. Thelight-emitting control lines are divided into a plurality of groups. Thedriving device includes a control circuit and a plurality of logicgates. The control circuit is configured to generate a globallight-emitting control signal and determine a duty cycle of the globallight-emitting control signal. The logic gates are coupled to thecontrol circuit to receive the global light-emitting control signal. Anoutput terminal of any one of the logic gates is configured to becoupled to the light-emitting control lines of a corresponding groupamong the groups, so as to determine whether to transmit the globallight-emitting control signal to the light-emitting control lines of thecorresponding group. When the global light-emitting control signal istransmitted to a corresponding light-emitting control line among thelight-emitting control lines, a pulse of the global light-emittingcontrol signal lights up a plurality of pixels connected to thecorresponding light-emitting control line.

An operation method of the invention includes: generating a globallight-emitting control signal and determining a duty cycle of the globallight-emitting control signal by a control circuit; determining whetherto transmit the global light-emitting control signal to thelight-emitting control lines of a corresponding group among a pluralityof groups by any one of the logic gates; and when the globallight-emitting control signal is transmitted to a correspondinglight-emitting control line among the light-emitting control lines,lighting up a plurality of pixels connected to the correspondinglight-emitting control line by a pulse of the global light-emittingcontrol signal.

To sum up, the control circuit provided by the embodiments of theinvention can generate the global light-emitting control signal anddetermine the duty cycle of the global light-emitting control signal. Anadjustment accuracy (resolution) of the duty cycle of the globallight-emitting control signal can be irrelevant to a line time of theOLED display panel.

For example, in some embodiments, an adjustment step of the duty cycleof the global light-emitting control signal can be smaller to a linetime of the OLED display panel.

To make the above features and advantages of the invention morecomprehensible, embodiments accompanied with drawings are described indetail below.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are included to provide a furtherunderstanding of the invention, and are incorporated in and constitute apart of this specification. The drawings illustrate embodiments of theinvention and, together with the description, serve to explain theprinciples of the invention.

FIG. 1 is a schematic circuit block diagram illustrating a displaydevice according to an embodiment of the invention.

FIG. 2 is a flowchart illustrating an operation method of a drivingdevice according to an embodiment of the invention.

FIG. 3 is a schematic timing diagram illustrating the signals depictedin FIG. 1 according to an embodiment of the invention.

FIG. 4 is a schematic timing diagram illustrating the signals depictedin FIG. 1 according to another embodiment of the invention.

FIG. 5 is a schematic circuit block diagram illustrating a displaydevice according to another embodiment of the invention.

FIG. 6 is a schematic circuit block diagram illustrating a displaydevice according to another embodiment of the invention.

DESCRIPTION OF EMBODIMENTS

The term “couple (or connect)” throughout the specification (includingthe claims) of this application are used broadly and encompass directand indirect connection or coupling means. For example, if thedisclosure describes a first device being coupled (or connected) to asecond device, then it should be interpreted that the first device canbe directly connected to the second device, or the first device can beindirectly connected to the second device through other devices or by acertain coupling means. Terms such as “first” and “second” mentionedthroughout the specification (including the claims) of this applicationare only for naming the names of the elements or distinguishingdifferent embodiments or scopes and are not intended to limit the upperlimit or the lower limit of the number of the elements not intended tolimit sequences of the elements. Moreover, elements/components/stepswith same reference numerals represent same or similar parts in thedrawings and embodiments. Elements/components/notations with the samereference numerals in different embodiments may be referenced to therelated description.

FIG. 1 is a schematic circuit block diagram illustrating a displaydevice 10 according to an embodiment of the invention. The displaydevice 10 includes an organic light emitting diode (OLED) display panel11 and a driving device 100. In the embodiment illustrated in FIG. 1,the driving device 100 includes a control circuit 110 and a plurality oflogic gates 120. The OLED display panel 11 has a plurality oflight-emitting control lines, for example, light-emitting control linesEML1 and EML2. The driving device 100 may drive the light-emittingcontrol lines of the OLED display panel 11 to light up a plurality ofpixel units (not shown) connected to the light-emitting control lines.The implementation manner of the OLED display panel 11 is not limited inthe present embodiment. Based on a design requirement, in someembodiments, the OLED display panel 11 may be a conventional OLEDdisplay panel or other OLED display panels.

The light-emitting control lines of the OLED display panel 11 aredivided into a plurality of groups. For example, the light-emittingcontrol lines of the OLED display panel 11 are divided into groups EMG1,EMG2, EMG3, EMG4, EMG5, EMG6, . . . , EMGn−1 and EMGn. The number n ofthe groups may be determined based on a design requirement. If it isassumed that the number of the light-emitting control lines of the OLEDdisplay panel 11 is N, the number n of the groups may be less than orequal to the number N of the light-emitting control lines.

FIG. 2 is a flowchart illustrating an operation method of a drivingdevice according to an embodiment of the invention. Referring to FIG. 1and FIG. 2, the control circuit 110 may generate a global light-emittingcontrol signal EM and determine a duty cycle of the globallight-emitting control signal EM (step S210). An adjustment accuracy(resolution) of the duty cycle of the global light-emitting controlsignal EM may be irrelevant to a line time of the OLED display panel 11.For example, in some embodiments, an adjustment step of the duty cycleof the global light-emitting control signal EM may be smaller to a linetime of the OLED display panel 11.

The logic gates 120 are coupled to the control circuit 110 to receivethe global light-emitting control signal EM. An output terminal of anyone of the logic gates 120 is configured to be coupled to thelight-emitting control lines of a corresponding group among the groupsEMG1 to EMGn of the OLED display panel. Any one of the logic gates 120may determine whether to transmit the global light-emitting controlsignal EM to the light-emitting control lines of the corresponding groupamong the groups EMG1 to EMGn (step S220).

When the global light-emitting control signal EM is transmitted to acorresponding light-emitting control line among the light-emittingcontrol lines of the OLED display panel 11, a pulse of the globallight-emitting control signal EM may light up a plurality of pixelsconnected to the corresponding light-emitting control line (step S230).Otherwise, when the global light-emitting control signal EM is blockedfrom the corresponding light-emitting control line, the pixels connectedto the corresponding light-emitting control line are incapable of beinglit (i.e., the pixels are maintained in a non-lighting state).

In the embodiment illustrated in FIG. 1, the logic gates 120 includemultiplexers 121_1, 121_2, 121_3, 121_4, 121_5, 121_6, . . . , 121_n−1and 121_n. An output terminal of the multiplexer 121_1 is configured tobe coupled to the light-emitting control lines (e.g., the light-emittingcontrol lines EML1 and EML2) of the group EMG1 (a corresponding group)among the groups EMG1 to EMGn. An input terminal of the multiplexer121_1 is coupled to the control circuit 110 to receive the globallight-emitting control signal EM. A control terminal of the multiplexer121_1 is coupled to the control circuit 110 to receive a control signalCS1. Based on the control of the control signal CS1 of the controlcircuit 110, the multiplexer 121_1 may determine whether to transmit theglobal light-emitting control signal EM to the light-emitting controllines (e.g., the light-emitting control lines EML1 and EML2) of thegroup EMG1.

The rest of the multiplexers 121_2 to 121_n may be inferred withreference to the description related to the multiplexer 121_1 and thus,will not be repeated. Based on the control of control signals CS1, CS2,CS3, CS4, CS5, CS6, . . . , CSn−1 and CSn of the control circuit 110,each of the multiplexers 121_1 to 121_n may determine whether totransmit the global light-emitting control signal EM to thelight-emitting control lines of the corresponding group among the groupsEMG1 to EMGn.

FIG. 3 is a schematic timing diagram illustrating the signals depictedin FIG. 1 according to an embodiment of the invention. The lateral axisillustrated in FIG. 3 represent the time. As illustrated in FIG. 3,Vsync1 represents an external vertical synchronization signal, andVsync2 represents an internal vertical synchronization signal. Thevertical synchronization signal Vsync1 may define a frame period. Aframe period includes a front porch period VFP and a back porch periodVBP.

Referring to FIG. 1 and FIG. 3, a frame period is divided into aplurality of sub periods, for example, sub periods P1 and P2. During thesub period P1, a logic gate (e.g., the multiplexer 121_2) among thelogic gates 120 blocks the global light-emitting control signal EM frombeing transmitted to the light-emitting control lines of a correspondinggroup (e.g., the group EMG2) among the groups EMG1 to EMGn. During thesub period P2, the same logic gate (e.g., the multiplexer 121_2) maytransmit the global light-emitting control signal EM to thelight-emitting control lines of the corresponding group (e.g., the groupEMG2).

According to an actual operation of the system, a length of the frameperiod may be dynamically changed. Taking the embodiment illustrated inFIG. 3 for example, an end time point of the frame period is delayedfrom a time point T1 to a time point T2. Namely, the front porch periodVFP is additionally added by an extended front porch period EFP. Duringthis extended period (i.e., a period from the time point T1 to the timepoint T2), the control circuit 110 may continue providing the controlsignals CS1 to CSn and maintain the duty cycle of the globallight-emitting control signal EM to maintain a luminance of the OLEDdisplay panel 11.

FIG. 4 is a schematic timing diagram illustrating the signals depictedin FIG. 1 according to another embodiment of the invention. The lateralaxis illustrated in FIG. 4 represent the time. As illustrated in FIG. 4,Vsync1 represents an external vertical synchronization signal, andVsync2 represents an internal vertical synchronization signal. Thevertical synchronization signal Vsync1 may define a frame period. Aframe period includes a front porch period VFP and a back porch periodVBP. When a level of any one of the control signals CS1 to CSn is a lowlevel, a corresponding logic gate among the logical gates 120 is turnedoff. When a level of one of the control signals CS1 to CSn is a highlevel, a corresponding logic gate among the logical gates 120 is turnedon.

Referring to FIG. 1 and FIG. 4, a frame period is divided into aplurality of sub periods, for example, sub periods P1 and P2. During thesub period P1, a logic gate (e.g., the multiplexer 121_2) among thelogic gates 120 may block the global light-emitting control signal EMfrom being transmitted to the light-emitting control lines of acorresponding group (e.g., the group EMG2) among the groups EMG1 toEMGn. During the sub period P2, the same logic gate (e.g., themultiplexer 121_2) may transmit the global light-emitting control signalEM to the light-emitting control lines of the corresponding group (e.g.,the group EMG2).

FIG. 5 is a schematic circuit block diagram illustrating a displaydevice 50 according to another embodiment of the invention. The displaydevice 50 includes an OLED display panel 11 and a driving device 500.The OLED display panel 11 illustrated in FIG. 5 may be inferred withreference to the description related to the display panel 11 illustratedin FIG. 1 and thus, will not be repeated. In the embodiment illustratedin FIG. 5, the driving device 500 includes a control circuit 110 and aplurality of logic gates 130. The logic gates 130 illustrated in FIG. 5may be inferred with reference to the description related to the logicgates 120 illustrated in FIG. 1, and the control circuit 110 illustratedin FIG. 5 may be inferred with reference to the descriptions related tothe embodiments illustrated in FIG. 1 through FIG. 4, which will not berepeated.

In the embodiment illustrated in FIG. 5, the logic gates 130 include ANDgates 131_1, 131_2, 131_3, 131_4, 131_5, 131_6, . . . , 131_n−1 and131_n. An output terminal of the AND gate 131_1 is configured to becoupled to the light-emitting control lines (e.g., the light-emittingcontrol lines EML1 and EML2) of the group EM1 (a corresponding group)among the groups EMG1 to EMGn. A first input terminal of the AND gate131_1 is coupled to the control circuit 110 to receive the globallight-emitting control signal EM. A second input terminal of the ANDgate 131_1 is coupled to the control circuit 110 to receive the controlsignal CS1. Based on the control of the control signal CS1 of thecontrol circuit 110, the AND gate 131_1 may determine whether totransmit the global light-emitting control signal EM to thelight-emitting control lines (e.g., the light-emitting control linesEML1 and EML2) of the group EMG1.

The rest of the AND gates 131_2 to 131_n may be inferred with referenceto the description related to the AND gate 131_1 and thus, will not berepeated. Based on the control of the control signals CS1 to CSn of thecontrol circuit 110, each of the AND gates 131_1 to 131_n may determinewhether to transmit the global light-emitting control signal EM to thelight-emitting control lines of the corresponding group among the groupsEMG1 to EMGn.

FIG. 6 is a schematic circuit block diagram illustrating a displaydevice 600 according to another embodiment of the invention. The displaydevice 60 includes an OLED display panel 11 and a driving device 600.The OLED display panel 11 illustrated in FIG. 6 may be inferred withreference to the description related to the display panel 11 illustratedin FIG. 1 and thus, will not be repeated. In the embodiment illustratedin FIG. 6, the driving device 600 includes a control circuit 110 and aplurality of logic gates 140. The logic gates 140 illustrated in FIG. 6may be inferred with reference to the description related to the logicgates 120 illustrated in FIG. 1, and the control circuit 110 illustratedin FIG. 6 may be inferred with reference to the descriptions related tothe embodiments illustrated in FIG. 1 through FIG. 4, which will not berepeated.

In the embodiment illustrated in FIG. 6, the logic gates 140 includeswitches 141_1, 141_2, 141_3, 141_4, 141_5, 141_6, . . . , 141_n−1 and141_n. A first terminal of the switch 141_1 is configured to be coupledto the light-emitting control lines (e.g., the light-emitting controllines EML1 and EML2) of the group EM1 (a corresponding group) among thegroups EMG1 to EMGn. A second terminal of the switch 141_1 is coupled tothe control circuit 110 to receive the global light-emitting controlsignal EM. A control terminal of the switch 141_1 is coupled to thecontrol circuit 110 to receive the control signal CS1. Based on thecontrol of the control signal CS1 of the control circuit 110, the switch141_1 may determine whether to transmit the global light-emittingcontrol signal EM to the light-emitting control lines (e.g., thelight-emitting control lines EML1 and EML2) of the group EMG1.

The rest of the switches 141_2 to 141_n may be inferred with referenceto the description related to the switch 141_1 and thus, will not berepeated. Based on the control of the control signals CS1 to CSn of thecontrol circuit 110, each of the switches 141_1 to 141_n may determinewhether to transmit the global light-emitting control signal EM to thelight-emitting control lines of the corresponding group among the groupsEMG1 to EMGn.

Based on different design demands, the block of the control circuit 110may be implemented in a form of hardware, firmware, software (i.e.,programs) or in a combination of many of the aforementioned three forms.

In terms of the hardware form, the block of the control circuit 110 maybe implemented in a logic circuit on an integrated circuit. Relatedfunctions of the control circuit 110 may be implemented in the hardwareform by utilizing hardware description languages (e.g., Verilog HDL orVHDL) or other suitable programming languages. For example, the relatedfunctions of the control circuit 110 may be implemented in one or morecontrollers, a micro-controller, a microprocessor, anapplication-specific integrated circuit (ASIC), a digital signalprocessor (DSP), a field programmable gate array (FPGA) and/or variouslogic blocks, modules and circuits in other processing units.

In terms of the software form and/or the firmware form, the relatedfunctions of the control circuit 110 may be implemented as programmingcodes. For example, the control circuit 110 may be implemented by usinggeneral programming languages (e.g., C or C++) or other suitableprogramming languages. The programming codes may be recorded/stored inrecording media, and the aforementioned recording media include, forexample, a read only memory (ROM), a storage device and/or a randomaccess memory (RAM). The programming codes may be accessed from therecording medium and executed by a computer, a central processing unit(CPU), a controller, a micro-controller or a microprocessor toaccomplish the related functions. As for the recording medium, a“non-transitory computer readable medium”, such as a tape, a disk, acard, a semiconductor memory or a programming logic circuit, may beused. In addition, the programs may be provided to the computer (or theCPU) through any transmission medium (e.g., a communication network orradio waves). The communication network is, for example, the Internet,wired communication, wireless communication or other communicationmedia.

Based on the above, the control circuit provided by the embodiments ofthe invention can generate the global light-emitting control signal anddetermine the duty cycle of the global light-emitting control signal.The adjustment accuracy (resolution) of the duty cycle of the globallight-emitting control signal EM can be irrelevant to a line time of theOLED display panel. For example, in some embodiments, the adjustmentstep of the duty cycle of the global light-emitting control signal canbe smaller to a line time of the OLED display panel. The driving deviceprovided by the embodiments of the invention can drive the OLED displaypanel.

It will be apparent to those skilled in the art that variousmodifications and variations can be made to the structure of thedisclosed embodiments without departing from the scope or spirit of thedisclosure. In view of the foregoing, it is intended that the disclosurecover modifications and variations of this disclosure provided they fallwithin the scope of the following claims and their equivalents.

What is claimed is:
 1. A driving device, configured to drive a pluralityof light-emitting control lines of an organic light emitting diode(OLED) display panel, the light-emitting control lines being dividedinto a plurality of groups, and the driving device comprising: a controlcircuit, configured to generate a global light-emitting control signaland determine a duty cycle of the global light-emitting control signal;and a plurality of logic gates, coupled to the control circuit toreceive the global light-emitting control signal, wherein an outputterminal of any one of the logic gates is configured to be coupled tothe light-emitting control lines of a corresponding group among thegroups, so as to determine whether to transmit the global light-emittingcontrol signal to the light-emitting control lines of the correspondinggroup, wherein when the global light-emitting control signal istransmitted to a corresponding light-emitting control line among thelight-emitting control lines, a pulse of the global light-emittingcontrol signal lights up a plurality of pixels connected to thecorresponding light-emitting control line, and the control circuit isfurther configured to maintain the duty cycle of the globallight-emitting control signal to maintain a luminance of the OLEDdisplay panel during an extended front porch period after an end timepoint of a frame period.
 2. The driving device according to claim 1,wherein the frame period is divided into a plurality of sub periods, afirst logic gate among the logic gates blocks the global light-emittingcontrol signal from being transmitted to the light-emitting controllines of a first group among the groups during a first sub period amongthe sub periods, and the first logic gate transmits the globallight-emitting control signal to the light-emitting control lines of thefirst group during a second sub period among the sub periods.
 3. Thedriving device according to claim 1, wherein any one of the logic gatescomprises: a multiplexer, having an output terminal configured to becoupled to the light-emitting control lines of the corresponding groupamong the groups, wherein an input terminal of the multiplexer iscoupled to the control circuit to receive the global light-emittingcontrol signal, and a control terminal of the multiplexer is coupled tothe control circuit to receive a control signal.
 4. The driving deviceaccording to claim 1, wherein any one of the logic gates comprises: anAND gate, having an output terminal configured to be coupled to thelight-emitting control lines of the corresponding group among thegroups, wherein a first input terminal of the AND gate is coupled to thecontrol circuit to receive the global light-emitting control signal, anda second input terminal of the AND gate is coupled to the controlcircuit to receive a control signal.
 5. The driving device according toclaim 1, wherein any one of the logic gates comprises: a switch, havinga first terminal configured to be coupled to the light-emitting controllines of the corresponding group among the groups, wherein a secondterminal of the switch is coupled to the control circuit to receive theglobal light-emitting control signal, and a control terminal of theswitch is coupled to the control circuit to receive a control signal. 6.An operation method of a driving device configured to drive a pluralityof light-emitting control lines of an OLED display panel, thelight-emitting control lines being divided into a plurality of groups,and the operation method comprising: generating a global light-emittingcontrol signal and determining a duty cycle of the global light-emittingcontrol signal by a control circuit; determining whether to transmit theglobal light-emitting control signal to the light-emitting control linesof a corresponding group among the groups by any one of a plurality oflogic gates, wherein the logic gates are coupled to the control circuitto receive the global light-emitting control signal, and an outputterminal of the any one of the logic gates is configured to be coupledto the light-emitting control lines of the corresponding group among thegroups; maintaining the duty cycle of the global light-emitting controlsignal to maintain a luminance of the OLED display panel by the controlcircuit during an extended front porch period after an end time point ofa frame period; and when the global light-emitting control signal istransmitted to a corresponding light-emitting control line among thelight-emitting control lines, lighting up a plurality of pixelsconnected to the corresponding light-emitting control line by a pulse ofthe global light-emitting control signal.
 7. The operation methodaccording to claim 6, further comprising: dividing the frame period intoa plurality of sub periods; blocking the global light-emitting controlsignal from being transmitted to the light-emitting control lines of afirst group among the groups by a first logic gate among the logic gatesduring a first sub period among the sub periods; and transmitting theglobal light-emitting control signal to the light-emitting control linesof the first group during a second sub period among the sub periods. 8.The operation method according to claim 6, wherein any one of the logicgates comprises a multiplexer, an output terminal of the multiplexer isconfigured to be coupled to the light-emitting control lines of thecorresponding group among the groups, an input terminal of themultiplexer is coupled to the control circuit to receive the globallight-emitting control signal, and a control terminal of the multiplexeris coupled to the control circuit to receive a control signal.
 9. Theoperation method according to claim 6, wherein any one of the logicgates comprises an AND gate, an output terminal of the AND gate isconfigured to be coupled to the light-emitting control lines of thecorresponding group among the groups, a first input terminal of the ANDgate is coupled to the control circuit to receive the globallight-emitting control signal, and a second input terminal of the ANDgate is coupled to the control circuit to receive a control signal. 10.The operation method according to claim 6, wherein any one of the logicgates comprises a switch, a first terminal of the switch is configuredto be coupled to the light-emitting control lines of the correspondinggroup among the groups, a second terminal of the switch is coupled tothe control circuit to receive the global light-emitting control signal,and a control terminal of the switch is coupled to the control circuitto receive a control signal.